Test structures are fabricated in order to enhance defect detection and/or analysis of micro-fabrication manufacturing process. Test structures may be included in a variety of objects, such as but not limited to integrated circuits, masks (for fabricating integrated circuits, flat panel displays and the like), MEMS devices and the like. They may be located at various locations on these objects, such as in the integrated circuit die or in scribe lines on semiconductor wafers.
In many cases the size of a defect is much smaller than the size of the test structure and the second stage of locating the defect is time consuming, especially in the context of integrated circuit manufacturing, and failure analysis devices, such as Defect Review Scanning Electron Microscope (DR-SEM) that are utilized during said manufacturing process.
Usually, test structures include one, two or more electrical conductors that may be shaped in various manners, such as a comb, serpentine, nest, via chain and the like that are known in the art. A defective test structure may be characterized by hard defects (electrical short or electrical open, i.e. isolated) and soft defects (high resistance vias or shorts resulting from metal threads or stringers).
Various devices exist for defect detection and defect analysis. A tester can perform various electrical tests by connecting a probe card to a test structure. A typical probe card includes multiple pins and can perform complex electrical tests.
A defect localization system locates defects, usually after the tester finds defective test structures, and usually uses a small and simple prober. A prober has typically two needles, and being small, it is used for simple functions (such as resistance measurement). Due to its small size it does not substantially interfere with test structure imaging. Defect analysis devices usually mill defects or their vicinity.
Some prior art defect localization methods require to connect a tested wafer to a probe card and also to be inspected. These prior art methods can involve using an electrical beam, a laser beam, an infra-red beam and the like.
Various vendors offer testing devices that include probe cards. These vendors include, for example, Cascade Microtech Inc. of the United States, SV Probe of San Jose, Calif., and the like.
The following U.S. patents and patent applications provide a brief overview of state of the art probe cards: U.S. Pat. Nos. 6,563,330 and 6,774,650 of Maruyama et al., titled “Probe card and method of testing wafer having a plurality of semiconductor devices”; U.S. Pat. No. 6,642,729 of Kang et al., titled “Probe card for tester head”; U.S. Pat. No. 6,714,828 of Eldridge et al., titled “Method and system for designing a probe card”; and U.S Pat. No. 6,788,082 of Hirao titled “probe card”.
FIG. 1 illustrates a prior art probe card 10. The round-shaped probe card 10 includes multiple pins (usually between thirty two pins and two hundred and fifty two pins) 20 that are located at small pins area 22 that is positioned at the center of probe card 10. These pins 20 are connected by multiple connectors 24 to large probe card pads 26. The large probe card pads 26 are located near the perimeter of the probe card 10. The multiple connectors 24 define an annular area 28 that is usually much larger than the pins area 22. The large probe card pads are contacted by connectors of a dedicated tester device that can read signals and provide signals via these pads.
FIG. 2 illustrates a typical test structure array 30. Test structure array 30 includes two columns of test structures (collectively denoted 34 and 134) and two columns of test structure pads (collectively denoted 32 and 132). Each test structure is connected to a small test structure pad that in turn is designed such to make contact with a pin out of multiple pins 20 of the probe card 10. The two columns of test structure pads 32 and 132 are located at the center of the test structure array 30.
During a defect localization process, the test structures should be scanned while the corresponding test structure pads should be connected to pins 20 in order to receive appropriate voltage.
FIG. 3 is a cross sectional view of a probe card 10 of FIG. 1 that is connected to the test structure array 30 of FIG. 2. As can seen by FIG. 3, when the pins in pin area 22 are connected to the test structure pads 32 and/or 132 the probe card 10 blocks scanning beams, and thus prevents the imaging of relatively large areas of the test structure array 30 which are adjacent to the test structure pads.
There is a need to provide a probe card and a method for allowing efficient defect localization.